Apple patents involve level shifter, NBTI reduction techniques, more
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Apple patents involve level shifter, NBTI reduction techniques, more

Several Apple patents have appeared at the US Patent & Trademark Office. Following is a summary of each.

Patent number 7994820 is for a level shifter with embedded logic and low minimum voltage. Per the patent, in one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output.

Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. The inventors are Brian J. Campbell, Vincent R. von Kaenel, Naveen Javarapopa and Greg M. Hess.

Patent number 7995410 involves leakage and NBTI reduction techniques for memory. Per the patent, in one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein).

If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion. The inventors are Brian J. Campbell, Greg M. Hess and Hang Huang.

Patent number 79966460 is for fly-by and ack-accelerated arbitration for broadcast packets. A method for administering transmission of a first type of packets and a second type of packets over a serial bus is disclosed. In one embodiment, the method comprises: if there is a packet of a second type to be sent, then concatenating the packet of the second type to a plurality of packets of the first type and sending the plurality of packets of the first type followed by the concatenated packet of the second type; and if there is no packet of the second type to be sent, then concatenating a bogus ack packet to the plurality of packets of the first type and sending the plurality of packets of the first type followed by the concatenated bogus ack packet. The inventors are Jerrold V. Hauck, Prashant Kanhere and William S. Duckwall.

Patent number 79966460 involves efficient coding for detecting load dependency on store with misalignment. Per the patent, in one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges.

A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation. The inventors are Tse-yu Yeh, Daniel C. Murray, Po-Young Chang and Anup S. Mehta.

-- Dennis Sellers

 

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