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Intel reveals details of next-gen computing platforms


At this week’s SC11 conference in Seattle, Intel ( evealed details about the company’s next-generation Intel Xeon processor-based and Intel Many Integrated Core (Intel MIC)-based platforms designed for high-performance computing (HPC).

During his briefing at the conference, Rajeeb Hazra, general manager of Technical Computing, Intel Datacenter and Connected Systems Group, said that the Intel Xeon processor E5 family is the world’s first server processor to support full integration of the PCI Express 3.0 specification. PCIe 3.0 is estimated to double the interconnect bandwidth over the PCIe 2.0 specification while enabling lower power and higher density server implementations. New fabric controllers taking advantage of the PCI Express 3.0 specification will allow more efficient scaling of performance and data transfer with the growing number of nodes in HPC supercomputers, says Hazra.

The early performance benchmarks revealed that the Intel Xeon E5 delivers up to 2.1times more performance in raw FLOPS (Floating Point Operations Per Second as measured by Linpack) and up to 70% more performance using real-HPC workloads compared to the previous generation of Intel Xeon 5600 series processors.

During SC’11 Intel also provided details on its greatly expanded lineup of server boards and chassis, including products specifically optimized for HPC, which will be ready to support the launch of the Intel Xeon Processor E5.

Intel also reiterated its commitment to delivering the most efficient and programming-friendly platform for highly parallel applications. The benefits of the Intel MIC architecture in weather modeling, tomography, proteins folding and advanced materials simulation were shown at Intel’s booth at SC’11.

The first presentation of the first silicon of “Knights Corner” co-processor showed that Intel architecture is capable of delivering more than 1 TFLOPs of double precision floating point performance (as measured by the Double-precision, General Matrix-Matrix multiplication benchmark — DGEMM), according to Hazra. This was the first demonstration of a single processing chip capable of achieving such a performance level, he adds.

Hazra said that the Knights Corner co-processor is very unique as, unlike traditional accelerators, it’s fully accessible and programmable like fully functional HPC compute node, visible to applications as though it was a computer that runs its own Linux-based operating system independent of the host OS.

One of the benefits of Intel MIC architecture is the ability to run existing applications without the need to port the code to a new programming environment, says Hazra. This will allow scientists to use both CPU and co-processor performance simultaneously with existing x86 based applications, dramatically saving time, cost and resources that would otherwise be needed to rewrite them to alternative proprietary languages, he adds.

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