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"Mac Memory Examined"

By Jeff Mitchell, President, Digital Solutions, MacTutor Contributing Editor

The Macintosh has been unique among personal computers in that it was the first computer introduced with a minimum of 128K Bytes of RAM that was immediately criticized for not having enough. The Fat Mac has quieted that criticism somewhat, and there are rumors of even more memory upgrades coming. [Experience has now shown that the Mac design required a minimum of 512K RAM and 800K dual floppy drives to be really practical and friendly to the user. We have the memory now but the disk bound nature of the new application packages is making disk juggling a full time Mac occupation! Say, didn't the old "Flippy" Lisa drives support 800K? That early Mac design was right-on capacity wise. -Ed.]

In this article I will describe the basic internal architecture of dynamic RAM, explore the design tradeoffs that have led to the memory configuration and the data access techniques employed in the Macintosh, and describe the memory map with its various screen, sound, and disk speed buffers.

More dynamic RAMs are sold than any other type of semiconductor device in the world. This is due to two major factors. First, the demand by computer manufacturers for inexpensive, high density memory. Secondly, semiconductor manufacturers use dynamic RAMs as a testbed for their IC process technology. The very regular structure of one memory cell repeated thousands of times, plus the very high demand for these devices allow the manufacturers to develop new, smaller device geometries with reasonably low risk and then use the large demand to speed the improvement of production yields. Once the technology has been refined, it is used to develop other products. Semiconductor manufacturers have admitted to being in the dynamic RAM market not necessarily to make money, but only to break even, in order to have this development vehicle available to them.

Each bit in a dynamic RAM consists of a transistor and a capacitor. This is why such very high densities can be attained, since each individual cell is so small. In contrast, each bit in a static RAM consists of four or six transistors, arranged to form a latch. Since each cell in a static RAM is about 4 times as large as in a dynamic RAM, static RAMs lag about one generation behind dynamic RAMs in density (e.g. 64K static RAMs became available about the time 256K dynami Q-and-Ath dynamic RAMs, the capacitor used as the memory element is not perfectly insulated, allowing the charge to leak off over time. Thus it may at some point actually change state unless the charge is restored. The charge can be restored by performing either a read or write operation on the cell. This process is called refreshing and must be performed on all cells every 2 milliseconds with most 64K RAMs, or every 4 milliseconds with 265K RAMs.

Internally, the memory cells are arranged in a matrix of rows and columns. The intersection of a row address and a column address selects a single cell. Dynamic RAMs are usually packaged in a 16 pin package, which means the addresses must be multiplexed due to pin limitations. First the row addresses are presented along with the row address strobe (RAS), then the column addresses and the column address strobe (CAS) some time later. A very important advantage to the matrix configuration is that when a particular row is accessed, all the cells on that row are refreshed; each cell does not have to be refreshed individually.

The RAM in the Macintosh is shared between the processor and the screen, rather than the screen having a separate RAM area of its own. This is both a blessing and a curse. The blessing is that the screen accesses are frequent enough that there is no need for special circuitry to keep the RAM refreshed. The curse is that the processor is denied access to the RAM about 34% of the time while the screen is being refreshed.

The display RAM is bit-mapped, meaning that for each pixel on the screen there is a corresponding bit in memory. As the electron beam sweeps across the CRT, it is turned on or off depending upon the state of the bit assigned to that pixel (1 = off, or black; 0 = on, or white).

How can both the screen and the processor use the same RAM? The Macintosh memory design uses a standard technique called interleaving, where the screen and the processor alternate having access to the memory. Since the screen cannot be denied access, the processor must wait if there is a potential memory conflict (Figure 1). This type of RAM configuration is known as dual-port, where there are two independent and (seemingly) non-conflicting paths into the same memory area.

There are actually two screen buffers in RAM. The main buffer located at $7A700 ($1A700 in a 128K Mac), and an alternate buffer located at $72700 ($12700). Port A bit 6 of the 6522 VIA (Versatile Interface Adapter) is factored into the address decoding logic for the screen RAM and determines which buffer will be displayed. Figure 2 graphically describes the memory map and Figure 3 is a table showing the address location and effect on the memory map of VIA Port A.

In addition to the screen memory, the RAM also has a dedicated area set aside for the sound/disk speed buffer. This is accessed at the end of every horizontal retrace period and supplies an 8 bit value to the sound generator PWM (pulse width modulator) and a 6 bit value which is used to control disk motor speed. Again, as with the screen RAM, there is a main and alternate buffer at $7FD00 ($1FD00) and $7A100 ($1A100) respectively.

The memory access scheme for the ROM is much simpler than that of the RAM, since only the processor needs access to it. It is located at $400000 in both 512K and 128K Macs, and extends to $40FFFF (64K Bytes). ROM accesses always occur at full speed, with no wait states.

The ROM upgrade, rumored to be out this fall, expands the size of the ROM to 128K. It is interesting to note that the two ROMs are the only chips that are in sockets, suggesting that Apple foresaw this eventual need to revise and expand the ROMs. Unfortunately, any additional upgrades beyond 128K can only enhance and/or debug the ROM code unless there is (once again, as with the 256K RAMs) a new circuit board, since the ROM sockets cannot accommodate devices larger than 64K x 8 (there are two ROMs, making 128K total).

As with the screen and sound/disk speed buffers, there is a bit which affects the mapping of the entire RAM and ROM. The overlay bit (Figure 3) remaps the ROM to $000000 and the RAM to $600000 on reset. This is because the first four bus cycles after a reset, the 68000 fetches the supervisor stack pointer and the program counter from memory location $000000. This is where the RAM resides, but it contains invalid data at reset, so the ROM is placed there temporarily. After the exception tables are initialized and everything is set up, the overlay bit is cleared and the memory map returns to its normal configuration.

The electrical design of the Macintosh is elegant, although following in Apple tradition, is somewhat simplistic. For example, the address decoding for write operations to the 8530 SCC (Serial Communications Controller) relies on the 68000 to place the 8 bits of data on the high byte of the data bus when it is actually doing a write to the low byte. This it does, but Motorola warns that this is "a result of current implementation and may not appear on future devices." Apple is obviously gambling that Motorola won't change the implementation and that any parts they may buy from another source will perform identically. The benefit here is that the fewer the number of parts, the less there is to break and the cheaper the product is to manufacture.

Stay tuned for more Mac hardware, including future Apple Bus construction projects! If you have questions are ideas for future hardware topics, please share them with us. Write "The Electrical Mac" care of MacTutor.

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